1. Field of the Invention
This invention relates to the field of electronics packaging, and in particular, to high-density electronic modules for housing and interconnecting electronic components located on stacked substrate layers.
2. Description of the Related Art
Increasing the volume density of electronic packaging is crucial for reducing device sizes for a given functionality. Efforts to provide high-density electronic packaging have included three-dimensional stacking technology in an attempt to avoid the inherent geometric constraints of standard two-dimensional semiconductor integrated circuits (“ICs”). By stacking electronic modules on top of one another and providing interconnections between the modules, the multiple layers can provide additional circuit elements without extending the two-dimensional footprint beyond that of a single module. Certain embodiments have also included heat-conducting, electrically insulating layers to improve heat dissipation during operation of these stacked electronic modules.
Numerous packaging schemes have been developed for stacking silicon-based ICs to increase the volume densities of electronic devices. However, while the silicon wafers of the silicon-based ICs provide rigidity and stability for the electronic elements, the ultimate volume densities of the multilayer stacks are inherently limited due to the thicknesses of the silicon wafers. Lapping off excess silicon from the back side of silicon wafers before stacking has been used to decrease the thickness of the silicon layers, and hence increase the number of layers per unit height. However, this procedure is time-consuming and requires precise machining to avoid damaging the circuit elements.